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M470L3224DT0
200pin DDR SDRAM SODIMM
256MB DDR SDRAM MODULE
(32Mx64 based on 16Mx 16 DDR SDRAM)
200pin SODIMM 64bit Non-ECC/Parity
Revision 0.1 Jan. 2002
Rev. 0.1 Jan. 2002
M470L3224DT0
Revision History
Revision 0.0 (Dec. 2001)
1. First release.
200pin DDR SDRAM SODIMM
Revision 0.1 (Jan, 2002)
1. Added tRAP(Active to Read w/ autoprecharge command)
Rev. 0.1 Jan. 2002
M470L3224DT0
200pin DDR SDRAM SODIMM
M470L3224DT0 200pin DDR SDRAM SODIMM 32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16
GENERAL DESCRIPTION
The Samsung M470L3224DT0 is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M470L3224DT0 consists of eight CMOS 16M x 16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOPII(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M470L3224DT0 is Dual In-line Memory Modules and intended for mounting into 200pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. Max Freq. Interface M470L3224DT0-C(L)B3 166MHz(6ns@CL=2.5) M470L3224DT0-C(L)A2 133MHz(7.5ns@CL=2) M470L3224DT0-C(L)B0 133MHz(7.5ns@CL=2.5) M470L3224DT0-C(L)A0 100MHz(10ns@CL=2) * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V SSTL_2
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1250 mil, double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS Key DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 Pin Front Pin Front Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS Key DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 Pin 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 Back DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /S1 DU VSS DQ36 DQ37 VDD DM4 Pin 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 67 DQ27 135 DQ34 69 VDD 137 VSS 71 CB0 139 DQ35 73 CB1 141 DQ40 75 VSS 143 VDD 77 DQS8 145 DQ41 79 CB2 147 DQS5 81 VDD 149 VSS 83 CB3 151 DQ42 85 DU 153 DQ43 87 VSS 155 VDD 89 CK2 157 VDD 91 /CK2 159 VSS 93 VDD 161 VSS 95 CKE1 163 DQ48 97 DU 165 DQ49 99 A12 167 VDD 101 A9 169 DQS6 103 VSS 171 DQ50 105 A7 173 VSS 107 A5 175 DQ51 109 A3 177 DQ56 111 A1 179 VDD 113 VDD 181 DQ57 115 A10/AP 183 DQS7 117 BA0 185 VSS 119 /WE 187 DQ58 121 /S0 189 DQ59 123 DU(A13) 191 VDD 125 VSS 193 SDA 127 DQ32 195 SCL 129 DQ33 197 VDDSPD 131 VDD 199 VDDID 133 DQS4
PIN DESCRIPTION
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CK0~ CK2, CK0~ CK2 CKE0 CS0 RAS CAS WE DM0 ~ DM7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID NC * Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VDD identification flag No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Jan. 2002
M470L3224DT0
FUNCTIONAL BLOCK DIAGRAM
S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
BA0 - BA1 A0 - A13 RAS CAS CKE0 CKE1 WE V DDSPD V DD/V DDQ
200pin DDR SDRAM SODIMM
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D0
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D4
DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D2
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D6
S
D1
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
S
D5
DQS6 DM6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS7 DM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S
D3
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
Dram1
S
D7
BA0-BA1: DDR SDRAMs D0 - D7 A0-A13: DDR SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D3 CKE: SDRAMs D4 - D7 WE: SDRAMs D0 - D7 SPD D0 - D7 SCL WP SDA A0 SA0 A1 SA1 A2 SA2 Serial PD Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Clock Wiring SDRAMs 4 SDRAMs 4 SDRAMs NC CK CK Card Edge *Clock Net Wiring
R=120 5%
Dram2 Dram3 Dram4
VREF VSS
D0 - D7 D0 - D7
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 Jan. 2002
M470L3224DT0
Absolute Maximum Rate
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
200pin DDR SDRAM SODIMM
Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 12 50
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.35 2 5
Unit
Note
V V V V V V V V uA uA mA mA mA mA 3 5 1 2 4 4
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 Jan. 2002
M470L3224DT0
DDR SDRAM IDD spec table
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 580 720 24 200 160 280 440 1020 980 940 24 12 1620
200pin DDR SDRAM SODIMM
A2(DDR266@CL=2) B0(DDR266@CL=2.5) 500 640 24 160 144 240 360 860 800 840 24 12 1380
A0(DDR200@CL=2) 460 580 24 144 128 200 320 760 680 760 24 12 1200
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C)
Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5 * VDDQ 1.5 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit Unit V V V V V Note
Rev. 0.1 Jan. 2002
M470L3224DT0
200pin DDR SDRAM SODIMM
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25C, f=1MHz)
Parameter Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE ) Input capacitance(CKE0) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK1) Data & DQS input/output capacitance(DQ0~DQ63) Input capacitance(DM0~DM8) Symbol CIN1 CIN2 CIN3 CIN4 COUT CIN5 Min 36 36 26 34 12 12 Max 44 44 30 38 14 14 Unit pF pF pF pF pF pF
Rev. 0.1 Jan. 2002
M470L3224DT0
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
200pin DDR SDRAM SODIMM
-TCB3 (DDR333) Min
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
Symbol
-TCA2 (DDR266A) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TCB0 (DDR266B) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TCA0 (DDR200) Min
70 80 48 20 20 15 15 1 1 10 12 120K
Unit Note
ns ns ns ns ns ns ns tCK tCK ns ns 5 5
Max
Max
Max
Max
0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 1.1 1.1 -0.8 -0.8 0.5 0.5 1.0 0.67
0.55 0.55 +0.8 +0.8 0.6 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 2 5
1.1
tCK ns ns ns ns 6 6 6 6
+0.8 +0.8
ns ns V/ns V/ns 6 7 10
4.5 1.5
V/ns
Rev. 0.1 Jan. 2002
M470L3224DT0
-TCB3 (DDR333) Min
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP 0.4 18 (tWR/tCK) + (tRP/tCK) 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
200pin DDR SDRAM SODIMM
-TCA2 (DDR266A) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
Parameter
Symbol
-TCB0 (DDR266B) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6
-TCA0 (DDR200) Min
16 0.6 0.6 2.5 2 10 80 200 7.8 tHP -tQHS tCLmin or tCHmin 0.8 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit Note
ns ns ns ns ns ns ns tCK us ns ns ns tCK 3 1 5 4 7,8,9 7,8,9
Max
Max
Max
Max
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.1 Jan. 2002
M470L3224DT0
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50
200pin DDR SDRAM SODIMM
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
Rev. 0.1 Jan. 2002
M470L3224DT0
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS
200pin DDR SDRAM SODIMM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
RAS CAS WE BA0,1 A10/AP A12, A11 A9 ~ A0 Note
H H H
X X H L H X X
L L L L H L L
L L L H X L H
L L L H X H L
L L H H X H H V V
OP CODE OP CODE X
1, 2 1, 2 3 3 3 3
L H H
X Row Address L H L H X V X L H X
Column Address (A0~A9) Column Address (A0~A9)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 Jan. 2002
M470L3224DT0
PACKAGE DIMENSIONS
200pin DDR SDRAM SODIMM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.79 (20.00) 0.24 (6.0)
Full R 2x
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
2- 0.07 (1.80)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 16Mx16 SDRAM, TSOP SDRAM Part No. : K4H561638D
Rev. 0.1 Jan. 2002

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